Many integrated circuit memory devices include a plurality of banks of memory cells and column decoders therein which facilitate operations to write and read data to and from the banks of memory cells. As will be understood by those skilled in the art, such column decoders are typically responsive to a column address and a column selection control/enable signal which can be generated by a column selection signal controller. Block selectors may also be utilized to electrically couple an input/output bus to a respective column decoder. Such conventional multi-bank integrated circuit memory devices are more fully described at section 10.2.2 of a textbook by Jan M. Rabaey, entitled "Digital Integrated Circuits: A Design Perspective", Prentice-Hall, Inc. (1996).
FIG. 1 illustrates a conventional column selection signal controller having an input buffer 101, a pulse generator 103 and an output buffer 105 coupled in series. FIG. 2 is a timing diagram which illustrates operation of the signal controller of FIG. 1. The input buffer 101, which may comprise first and second serially connected inverters 121-122, receives a clock signal CLK at its input and generates an input control signal CPE at its output. The pulse generator 103 includes third through seventh inverters 123-127 and a NAND gate 131 having first and second inputs connected to an output of the seventh inverter 127 and the output of the second inverter 122. As will be understood by those skilled in the art, a series of 0.fwdarw.1 transitions by the input control signal CPE will cause the pulse generator 103 to generate a series of 1.fwdarw.0.fwdarw.1 pulses as signal CP. These pulses have a duration equal to the combined delay of the third through seventh inverters 123-127. The duration of each pulse is equal to t2, as illustrated by FIG. 2 and the duration t1+t2 equals the period of the clock signal CLK. The output buffer 105 includes eighth and ninth inverters 128-129 and generates a column selection enable signal CSLEN at its output.
As will be understood by those skilled in the art, read and write operations may be enabled when the column selection enable signal CSLEN is set to a logic 1 state and disabled when the column selection enable signal CSLEN returns to a logic 0 state. Thus, the duration t1 may determine the maximum available data access time during both read and write operations. Unfortunately, as integrated circuit memory devices are pushed to operate at higher and higher clock frequencies, the duration t1 may be sufficiently long to enable reliable reading of data from a column decoder, but not sufficiently long to enable reliable writing of data through a column decoder to a bank of memory cells coupled thereto. Such unreliability may be particularly severe when double data rate synchronous dynamic random access memory devices are employed. Thus, notwithstanding the above described integrated circuit memory devices, there continues to be a need for improved integrated circuit memory devices.